The present application relates to a data recovery circuit.
Program data or other data stored in a random-access memory (RAM) may include a soft error, which can occur due to various data damaging factors. To detect such an error in advance and prevent an erroneous system operation, a device that writes data to and reads data from the RAM performs parity checks. When a parity error is detected during a parity check, error correction is performed with firmware. However, the error correction using firmware requires a long processing time. Thus, a software error must be recovered more efficiently when performing a parity check.
A data recovery circuit that recovers data and has a parity check function adds a single parity bit to, for example, every byte of data in a RAM. During a writing operation, a data set of nine bits, which includes eight bits and a single parity bit added to the eight bits, is written to the RAM in a manner that the data set has, for example, an even number of bits of the value 1.
During a reading operation, the data set of nine bits undergoes a parity check to determine whether the data set has an even number of 1's. If the data stored in the RAM is damaged by a soft error, one bit of the data set would normally be inverted. Thus, the data set would have an odd number of 1's. In such a case, an error flag is generated, and an address at which the error has occurred is latched.
Subsequently, firmware is used to check the status of the error through interrupt processing and read the original data of the program data that includes the damaged data from an external memory, such as a flash memory. Then, the original data is rewritten to the RAM.
Japanese Laid-Open Patent Publication No. 2000-132461 describes an information control apparatus that regularly performs a parity error detection process for all program areas in a static random access memory (SRAM). When detecting a parity error, the information control apparatus rewrites data.
When an error is detected in program data that is stored in a RAM during a parity check, the data recovery circuit of the prior art must perform interrupt processing with an interrupt handler to entirely read the original program data from an external memory and rewrite the original data to the RAM. Therefore, the recovery process requires a long time.
Error correction may also be performed by adding an error checking and correcting (ECC) code to data. However, error correction using an ECC code requires an error correcting circuit. This would increase the circuit scale and as well as the access time.